View PI90LVB16L_8159665.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ps8536a 05/21/01 features ? master/slave clock selection in a backplane application ? 160 mhz operation (typical) ? 100ps duty cycle distortion (typical) ? 50ps channel to channel skew (typical) ? 3.3v power supply design ? glitch-free power on at clki/o pins ? low power design (16ma @ 3.3v static) ? accepts small swing (300mv typical) differential signal levels ? industrial temperature operating range (?40c to +85c) ? available in 24-pin tssop packaging (l) general description pi90lvb16 is a six-channel lvttl clock distribution driver with 50 picosecond channel-to-channel skew. it translates one blvds (bus low-voltage differential signaling) input signal into six lvttl- compatible output signals for distribution to adjacent chips on the same board. the pi90lvb16 accepts blvds (300mv typical) differ- ential input levels, and translates them to 3v cmos output levels. the 160mhz pi90lvb16 can be the master clock, driving inputs of other clock i/o pins in a multipoint environment. it can also drive the blvds backplane with a separate channel acting as a return/ source lvttl clock source. the master/slave clock selection of the driving source is controlled by the crdclk in and the de pins. an output enable pin oe, when high, forces all clk out pins high. a backplane clock distribution network must be able to drive many transmission line stubs. the bus lvds feature of the pi90lvb16 is ideal for driving data transfers in large, high-performance backplane system applications. the device can be used as a source synchro- nous driver to distribute clock signals within data and telecommu- nications systems. function diagram 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi90lvb16 3v bus lvds 1-to-6 clock buffer/bus transceiver delay mux clk out0 clk out1 clk out5 crdclk in d r de oe clki/0C clki/0+ receive mode truth table t u p n i t u p t u o e oe dk l c d r c n i ) ? o / i k l c ( ? ) + o / i k l c (k l c t u o hh x x h lh x d i v 3 v 7 0 . 0h lh x d i v v 7 0 . 0 ?l l = low logic state; h = high logic state; x = irrelevant z = high impedance t u p n it u p t u o e oe dk l c d r c n i + o / i k l c? o / i k l ck l c t u o ll l l h l ll h h l h hl l l h h hl h h l h hh x z z h driver mode truth table
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 2 ps8536a 05/21/01 pi90lvb16 3v bus lvds 1-to-6 clock buffer/bus transceiver gnd oe nc v cca gnda clki/0+ clki/0C gnda crdclk in nc de gnd v cc clk out0 gnd clk out1 v cc clk out2 gnd clk out3 v cc clk out4 gnd clk out5 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 connection diagram tssop package pin description 24-pin l e m a n n i p# n i pe p y tn o i t p i r c s e d + o / i k l c6o / i. t u p n i k c o l c l a i t n e r e f f i d e h t f o e d i s ) e v i t i s o p ( e u r t ? o / i k l c7o / i. t u p n i k c o l c l a i t n e r e f f i d e h t f o e d i s ) e v i t a g e n ( y r a t n e m e l p m o c e o2i k l c l l a s e c r o f n i p s i h t , h g i h n e h w . w o l e v i t c a s i n i p s i h t ; e o t u o , w o l n e h w . h g i h n i p k l c t u o o / i k l c e h t t a d i v r o n i k l c d r c e h t r e h t i e y b d e n i m r e t e d s i e t a t s c i g o l s n i p o t e c i v e d p u l l u p k a e w a s a h n i p s i h t . n i p e d e h t t a l e v e l c i g o l e h t o t t c e p s e r h t i w s n i p v c c k l c l l a n e h t , g n i t a o l f s i e o f i . t u o . h g i h e b l l i w s n i p e d1 1i k l c d r a c e h t s e l b a n e n i p s i h t , w o l n e h w . w o l e v i t c a s i n i p s i h t ; e d n i e h t o t l a n g i s k l c d n a s n i p o / i k l c t u o e r a s n i p o / i k l c e h t , e t a t s - 3 s i r e v i r d e h t h g i h n e h w . k l c e h t f o e t a t s e h t e n i m r e t e d d n a s t u p n i t u o o t e c i v e d p u l l u p k a e w a s a h n i p s i h t . s n i p v c c . e t a t s - 3 e r a s n i p o / i k l c l l a n e h t , g n i t a o l f s i e d f i . k l c t u o 3 2 , 1 2 , 9 1 , 7 1 , 5 1 , 3 1o . s t u p t u o ) s o m c ( k c o l c d e r e f f u b x i s k l c d r c n i 9i . ) l e v e l l t t r o l e v e l s o m c ( d r a c m o r f k c o l c t u p n i v c c 4 2 , 0 2 , 6 1r e w o pv c c v g o l a n a ; a c c v m o r f e t a r a p e s y l l a n r e t n i ( c c e t a r a p e s e s u r o y l l a n r e t x e t c e n n o c , v r e h t i e . d e r i u q e r g n i c n e u q e s r e w o p l a i c e p s o n . ) s e i l p p u s r e w o p a c c v r o c c e b n a c . s e i l p p u s r e w o p h t o b y l p p a y l s u o e n a t l u m i s r o , t s r i f d e i l p p a d n g2 2 , 8 1 , 4 1 , 2 1 , 1d n u o r gd n g v a c c 4r e w o pv g o l a n a a c c v m o r f e t a r a p e s y l l a n r e t n i ( c c r e w o p e t a r a p e s e s u r o y l l a n r e t x e t c e n n o c , v r e h t i e . d e r i u q e r g n i c n e u q e s r e w o p l a i c e p s o n . ) s e i l p p u s a c c v r o c c d e i l p p a e b n a c . s e i l p p u s r e w o p h t o b y l p p a y l s u o e n a t l u m i s r o , t s r i f a d n g8 , 5d n u o r g . y l l a n r e t x e d e t c e n n o c e b t s u m d n u o r g m o r f e t a r a p e s y l l a n r e t n i ( d n u o r g g o l a n a c n0 1 , 3 . s t c e n n o c o n
3 ps8536a 05/21/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi90lvb16 3v bus lvds 1-to-6 clock buffer/bus transceiver supply voltage range, v cc ..................................................................................... ?0.3v to +4v enable input voltage (de, oe, crdclk in ) .............................................. ?0.3v to +4v voltage (clk out ) ............................................................... ?0.3v to (v cc + 0.3v) voltage (clki/o) ............................................................... ?0.3v to (v cc + 0.3v) driver short circuit current ....................................................................... momentary receiver short circuit current .................................................................. momentary maximum package power dissipation at +25c tssop package ................................................................................... 1500mw derate tssop package ..................................................... 8.2mw/c above +25c q ja ............................................................................................................................... ............ 95c/w q jc ............................................................................................................................... ............ 30c/w storage temperature range ............................................................. ?65c to +150c lead temperature range (soldering, 4s) ........................................................... 260c esd ratings: hbm (2) .................................................................................................................. 9kv clk out(0?5) .......................................................................................................................... 3 2kv cdm (2) ............................................................................................................................... ... >1000v machine model (2) ............................................................................................................... >200v absolute maximum ratings (1) recommended operating conditions min. typ. max units supply voltage (v cc) +3.0 +3.3 +3.6 v crdclk in , de, oe input voltage 0 v cc v operating free air temperature (t a ) ?40 24 +85 c
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 4 ps8536a 05/21/01 pi90lvb16 3v bus lvds 1-to-6 clock buffer/bus transceiver dc electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specificed (3,4) l o b m y sr e t e m a r a ps n o i t i d n o cn i p. n i m. p y t. x a ms t i n u v h t h g i h d l o h s e r h t t u p n i , + o / i k l c ? o / i k l c 5 25 7 v m v l t w o l d l o h s e r h t t u p n i 0 7 ?5 3 ? r m c v e g a t l o v e d o m n o m m o c e g n a r ) 5 ( k a e p - o t - k a e p v m 0 5 2 = d i v ? v d i ? 2 / ? 8 . 2 ? v d i ? 2 / v i n i t n e r r u c t u p n i v n i v o t v o = c c v = e d , c c v = e o , c c , v m 0 5 v 2 . 1 = t u p n i r e h t o 0 1 ?5 0 1 +a v r 1 h o e g a t l o v h g i h t u p t u oi , v m 0 5 2 = d i v h o a m 0 . 1 ? = k l c t u o v c c 2 . 0 ?9 . 2 v v r 2 h o e g a t l o v h g i h t u p t u oi , v m 0 5 2 = d i v h o a m 6 ? =v c c 6 . 0 ?5 . 2 v r 1 l o e g a t l o v w o l t u p t u o i l o v m 0 5 2 ? = d i v , a m 0 . 1 = 4 0 . 01 . 0 v r 2 l o e g a t l o v w o l t u p t u o i l o v m 0 5 2 ? = d i v , a m 6 = 02 2 . 04 . 0 i r h d o k l c t u o c i m a n y d t n e r r u c t u p t u o ) 6 ( v , v m 0 5 2 + = d i v t u o v = c c v 1 ? 6 1 ?4 2 ?4 3 ? a m i r l d o v , v m 0 5 2 ? = d i v t u o v 1 = 4 15 25 . 7 3 v h i e g a t l o v h g i h t u p n i , e o , e d k l c d r c n i 0 . 2v c c v v l i e g a t l o v w o l t u p n i d n g8 . 0 i h i t n e r r u c h g i h t u p n i v n i v = c c v 4 . 2 r o e d , e o 6 ?46 a i l i t n e r r u c w o l t u p n i v n i v 4 . 0 r o d n g = 0 2 ?1 10 2 + i d r c n i t n e r r u c t u p n i v n i v o t v 0 = c c v = e o , c c k l c d r c n i 5 ?5 v l c p m a l c e g a t l o v t u p n i i t u o a m 5 . 1 ? =, e d , e o k l c d r c n i 8 . 0 ?v i c c y l p p u s d a o l o n t n e r r u c , d e l b a n e s t u p t u o d e i l p p a d i v o n , v 0 = e d = e o k l c d r c n i v = c c , d n g r o n e p o = ) ( o / i k l c k l c t u o t i u c r i c n e p o = ) 5 : 0 ( v c c 0 1 a m i 1 c c y l p p u s d a o l o n t n e r r u c , d e l b a n e s t u p t u o n o m m o c r e v o d i v e g n a r e g a t l o v v = e d , d n g = e o c c , k l c d r c n i v = c c , d n g r o ) v 5 7 2 . 2 m c v v 5 2 1 . 0 ( v m 0 5 2 = d i v k l c t u o t i u c r i c n e p o = ) 5 : 0 ( 6 i d c c y l p p u s d e d a o l r e v i r d t n e r r u c , v 0 = e o = e d k l c d r c n i v = c c , d n g r o r l 5 . 7 3 = w + o / i k l c n e e w t e b k l c , ? o / i k l c d n a t u o t i u c r i c n e p o = ) 5 : 0 ( 6 11 2
5 ps8536a 05/21/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi90lvb16 3v bus lvds 1-to-6 clock buffer/bus transceiver l o b m y sr e t e m a r a ps n o i t i d n o cn i p. n i m. p y t. x a ms t i n u v d o l a i t n e r e f f i d t u p t u o r e v i r d e g a t l o v r l 5 . 7 3 = w 5 e r u g i f , v 0 = e d , + o / i k l c ? o / i k l c 0 5 20 5 30 5 4 v m d v d o v r e v i r d d o e d u t i n g a m e g n a h c 20 2 v s o e g a t l o v t e s f f o r e v i r d 1 . 1 5 2 . 15 . 1v d v s o e g a t l o v t e s f f o r e v i r d e g n a h c e d u t i t l u m 10 2v m v d h o h g i h t u p t u o r e v i r d 4 . 18 . 1 v v d l o w o l t u p t u o r e v i r d 8 . 05 0 . 1 i d 1 s o t r o h s l a i t n e r e f f i d r e v i r d t n e r r u c t i u c r i c ) 6 ( k l c d r c n i v = c c , d n g r o v 0 = e d , ) r e h t e g o t d e t r o h s s t u p t u o ( , v 0 = d o v 3 1 7 1 a m i d 2 s o t r o h s l a i t n e r e f f i d r e v i r d v o t t n e r r u c t i u c r i c c c ) 6 ( k l c d r c n i v = + o / i k l c , v 0 = e d , d n g = c c 1 17 1 i d 3 s o k l c d r c n i v = c c v = ? o / i k l c , v 0 = e d , c c 0 17 1 i d 4 s o t r o h s l a i t n e r e f f i d r e v i r d d n g o t t n e r r u c t i u c r i c ) 6 ( k l c d r c n i v = c c + o / i k l c , v 0 = e d , = v 0 5 1 ?7 1 ? i d 5 s o k l c d r c n i ? o / i k l c , v 0 = e d , d n g = = v 0 5 1 ?7 1 ? i f f o e g a k a e l f f o r e w o p t n e r r u c v c c v , n e p o r o v 0 = d e i l p p a v 6 . 3 =0 2 a dc electrical characteristics (continued) over supply voltage and operating temperature ranges, unless otherwise specifice d (3,4) switching characteristics differential receiver characteristics over supply voltage and operating temperature ranges, unless otherwise specificed (7,8) l o b m y sr e t e m a r a ps n o i t i d n o c. n i m. p y t ) 1 ( . x a ms t i n u t r d l h p k l c . w o l o t h g i h y a l e d n o i t a g a p o r p l a i t n e r e f f i d o / i k l c o t t u o c l f p 5 1 = v m 0 5 2 = d i v 2 & 1 s e r u g i f 3 . 16 . 28 . 3 s n t r d h l p k l c . h g i h o t w o l y a l e d n o i t a g a p o r p l a i t n e r e f f i d o / i k l c o t t u o 3 . 16 . 28 . 3 t r 1 k s n o i t r o t s i d e l c y c y t u d ) 0 1 ( , w e k s e s l u p ? l h p t ? h l p t ? 50 0 4 s p t r 2 k s e g d e e m a s ; w e k s l e n n a h c - o t - l e n n a h c ) 1 1 ( 50 8 t r 3 k s w e k s t r a p - o t - t r a p ) 2 1 ( d b t s n t r h l t h g i h - o t - w o l e m i t n o i t i s n a r t ) 9 ( ) % 0 8 o t % 0 2 ( ,0 . 14 . 14 . 2 t r l h t w o l - o t - h g i h e m i t n o i t i s n a r t ) 9 ( ) % 0 2 o t % 0 8 ( ,0 . 13 . 14 . 2 t r e o h l p k l c o t e o ( h g i h - o t - w o l y a l e d n o i t a g a p o r p t u o ) c l f p 5 1 = 4 & 3 s e r u g i f 0 . 11 . 22 . 3 t r e o l h p k l c o t e o ( w o l - o t - h g i h y a l e d n o i t a g a p o r p t u o )0 . 11 . 22 . 3 f x a m y c n e u q e r f g n i t a r e p o m u m i x a m ) 5 1 ( 0 0 10 6 1z h m
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 6 ps8536a 05/21/01 pi90lvb16 3v bus lvds 1-to-6 clock buffer/bus transceiver switching characteristics differential driver timing requuirements ( over supply voltage and operating temperature ranges, unless otherwise specificed (7,8) notes: 1. ?absolute maximum ratings? are those values beyond which the safety of the device cannot be guaranteed. these ratings are not meant to imply that the devices should be operated at these limits. the table of ?electrical characteristics? specifies conditions of device operation. 2. esd rating: esd qualification is performed per the following: hbm (1.5k w , 100pf), machine model (250v, 0 w ), iec 1000-4-2. all v cc pins connected together, all ground pins connected together. 3. current into device pins are defined as positive. current out of device pins defined as negative. all voltages are referenced to ground except vid, vod, vth, and vtl 4. all typicals are given for: v cc = +3.3v and t a = +25c. 5. the vcmr range is reduced for larger vid. example: if vid=400 mv, then vcmr is 02v to 2.2vavid up to ? v cc -0v ? may be applied between the clki/o+ and clki/o? inputs, with the common mode set to v cc /2. 6. only one output should be momentarily shorted at a time. do not exceed package power dissipation rating. 7. c l includes probe and fixture capacitance. 8. generator waveform for all tests unless otherwise specified: f = 25 mhz, zo = 50 w , t r = 1ns, t f = 1ns (10%?90%). to ensure fastest propagation delay and minimum skew, clock input edge rates should not be slower than 1ns/v; control signals not slower than 3ns /v. in general, the faster the input edge rate, the better the ac performance, 9. all device output transition times are based on characterization measurements and are guaranteed by design. 10. t skir is the difference in receiver propagation delay ? t plh -t phl ? of one device, and is the duty cycle distortion of the output at any given temperature and v cc . the propagation delay specification is a device-to-device worst case over process, voltage and temperature. 11. t sk2r is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direc tion. this parameter is guaranteed by design and characterization. 12. t sk3r part-to-part skew, is the difference in receiver propagation delay between devices of any outputs switching in the same direct ion. this specification applies to devices over recommended operating temperature and voltage ranges, and across process distributio n. t sk3r is defined as max-min differential propagation delay. this parameter is guaranteed by design and characterization. 13. t sk1d is the difference in driver propagation delay ? t plh -t phl ? and is the duty cycle distortion of the clki/o outputs. 14. t sk2d part-to-part skew, is the difference in driver propagation delay between devices of any outputs switching in the same directio n. this specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t sk2d is defined as max-min differential propagation delay. 15. generator input conditions: t r t f < 1ns, 50% duty cycle, differential (1.10v to 1.35v pk-pk). output criteria: 60%/40% duty cycle, v ol (max) 0.4v, v oh (min) 2.7v, load - 7pf (stray plus probes). l o b m y sr e t e m a r a ps n o i t i d n o c. n i m. p y t ) 1 ( . x a ms t i n u t d d l h p k l c d r c . w o l o t h g i h y a l e d n o i t a g a p o r p l a i t n e r e f f i d n i o to / i k l c c l f p 5 1 = r l 5 . 7 3 = w 7 & 6 s e r u g i f 0 . 15 . 12 . 2 s n t d d h l p k l c d r c . h g i h o t w o l y a l e d n o i t a g a p o r p l a i t n e r e f f i d n i o to / i k l c0 . 13 . 12 . 2 t d r c l h p k l c d r c n i k l c o t t u o w o l o t h g i h y a l e d n o i t a g a p o r p c l f p 5 1 = 9 & 8 s e r u g i f 0 . 28 . 25 . 4 t d r c h l p k l c d r c n i k l c o t t u o h g i h o t w o l y a l e d n o i t a g a p o r p0 . 28 . 25 . 4 t d 1 k s w e k s l a i t n e r e f f i d ? t h l p t ? l h p ? ) 3 1 ( c l f p 5 1 = 7 & 6 s e r u g i f 0 0 6s p t d 2 k s w e k s t r a p - o t - t r a p l a i t n e r e f f i d ) 4 1 ( d b t s n t d h l t e m i t n o i t i s n a r t l a i t n e r e f f i d ) 9 ( ) % 0 8 o t % 0 2 ( ,2 . 05 3 . 05 6 . 0 t d l h t e m i t n o i t i s n a r t l a i t n e r e f f i d ) 9 ( ) % 0 2 o t % 0 8 ( ,2 . 05 3 . 05 6 . 0 t d z h p o / i k l c o t e d . e t a t s - 3 o t w o l e m i t n o i t i s n a r t v n i v o t v 0 = c c c l f p 5 1 = r l 5 . 7 3 = w 1 1 & 0 1 s e r u g i f 6 . 2 t d z l p o / i k l c o t e d . e t a t s - 3 o t w o l e m i t n o i t i s n a r t 6 . 2 t d h z p o / i k l c o t e d . h g i h - o t - e t a t s - 3 e m i t n o i t i s n a r t 3 . 4 t d l z p o / i k l c o t e d . w o l - o t - e t a t s - 3 e m i t n o i t i s n a r t 6 . 3 f x a m y c n e u q e r f g n i t a r e p o m u m i x a m ) 5 1 ( 0 0 10 6 1z h m
7 ps8536a 05/21/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi90lvb16 3v bus lvds 1-to-6 clock buffer/bus transceiver parameter measurement information v id = 250mv v oh v ol t plhdr t tlhr v cc /2 v cc /2 t thlr t phldr clki/0C clki/0+ clk out +1.35v 80% 80% 20% 20% +1.10v generator waveform for all test unless otherwise specificed: f = 25mhz, 50% duty cycle, z0 = 50 w , t thl = 1ns figure 1. receiver propagation delay and transition time test circuit figure 2. receiver propagation delay and transition time waveforms c l 50 w clk out clki/0+ clki/0C generator d.u.t.
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 8 ps8536a 05/21/01 pi90lvb16 3v bus lvds 1-to-6 clock buffer/bus transceiver figure 3. output enable (oe) test circuit figure 4. output enable (oe) delay waveforms oe t plhoer t phloer 50% s1C = 0.95v s1+ = 1.2v 50% 50% 50% clk out s1C = 0.95v s1+ = 1.2v clk out v oh v ol v oh v cc 0v parameter measurement information oe 0.95v 0.95v 1.2v + C generator 50 w c l test point test point clk out
9 ps8536a 05/21/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi90lvb16 3v bus lvds 1-to-6 clock buffer/bus transceiver crdclk in de d c l c l r l figure 6. driver propagation delay test circuit 2v 0.8v de d r l /2 = 18.75 w r l /2 = 18.75 w v os v od figure 5. differential driver dc test parameter measurement information figure 7. driver propagation delay and transition time waveforms t plhcrd 0 differential 0 differential t thldd t phldr crdclk in clki/0C clki/0+ v diff= [clki/)+] C [clki/)C] v cc v oh v ol 80% 50% 80% 20% 20% 0v t phlcrd t tlhdd
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 10 ps8536a 05/21/01 pi90lvb16 3v bus lvds 1-to-6 clock buffer/bus transceiver figure 8. crdclk in propagation delay time test circuit t plhcrd 50% 50% 50% 50% clk out clk in t phlcrd v ol v oh v cc 0v figure 9. crdclk in propagation delay time waveforms parameter measurement information c l 50 w clk out crdclk in generator d.u.t.
11 ps8536a 05/21/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi90lvb16 3v bus lvds 1-to-6 clock buffer/bus transceiver figure 10. driver 3-state test circuit crdclk in v cc pulse generator de 0v d c l c l r l /2 1.2v r l /2 50 w 1.2v de 0v v cc v ol v oh clki/o+ (crdclk in - l) clki/oC (crdclk in - h) clki/o+ (crdclk in -h) clki/oC (crdclk in - l) 1.2v 50% 50% 50% 50% 50% t plzd t pzld t pzhd t phzd figure 11. driver 3-state waveforms parameter measurement information
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 12 ps8536a 05/21/01 pi90lvb16 3v bus lvds 1-to-6 clock buffer/bus transceiver pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com 24-pin tssop (l) package ordering information e d o c g n i r e d r oe m a n e g a k c a pe p y t e g a k c a pe g n a r g n i t a r e p o l 6 1 b v l 0 9 i p4 2 lp o s s t n i p - 4 2c 5 8 o t c 0 4 ? .303 .311 .047 1.20 .002 .006 seating plane .0256 bsc .018 .030 .004 .008 .252 bsc 1 24 .169 .177 x.xx x.xx denotes controlling dimensions in millimeters 0.05 0.15 6.4 0.45 0.75 0.09 0.20 4.3 4.5 7.7 7.9 0.65 0.19 0.30 .007 .012 max

▲Up To Search▲

Price & Availability of PI90LVB16L

	To Download PI90LVB16L Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .